Conventionally, in a semiconductor device a wire bonding method is mainly used to connect electrode pads on a semiconductor chip and leads of the semiconductor package. For example, wire bonding technology is used in the semiconductor devices of patent document 1 (Japan Laid Open Patent H8-111495) and patent document 2 (Japan Laid Open Patent H-5-259208).
Here, wire bonding technology refers to connecting electrode pads and leads of a semiconductor package with a thin wire on a semiconductor chip obtaining an electrical connection.
In a semiconductor device which uses this wire bonding technology, as well as recent multi pin semiconductors and reduction in semiconductor chip size, fine pitch of electrode pads on a semiconductor chip, and lengthening and fine pitch of a wire in order to arrange multiple leads within the package are progressing.
However, when the length of a wire is increased and the pitch made finer, for example, the wire is transformed by the molded resin during a process for forming a resin package and adjacent wires may short. In addition, there is a limit to reducing the thickness of the entire package due to the loop height of a wire. Furthermore, a high level of positioning accuracy is required when accurately bonding a wire on a narrow electrode pad with a fine pitch.
The present invention provides a semiconductor device which has a high level of connection reliability, and is suited to miniaturization of electrode pads formed on a semiconductor chip.